(1) IF-UFRJ, Brazil
(2) EPFL, Switzerland
(3) CERN, Switzerland
(4) University of Glasgow, Kelvin Building, Glasgow G12 8QQ, Scotland.
The data from the VELO front-end is sent to the ADCs on the read-out board over a serial analogue link. Due to imperfections in the link, inter-symbol cross-talk occurs between adjacent time-bins in the transfer. This can be corrected by an Finite Impulse Response (FIR) filter implemented in the pre-processing FPGA located on the read-out board. This note reports on a method to determine the coefficients for the filter using data. Simulations are presented that show the performance of the method as it is implemented in the LHCb read-out board. The effectiveness of the algorithm is demonstrated by the improvements it brings in resolution on beam test data.